13th Int'l Symposium on Quality Electronic Design
نویسندگان
چکیده
Three dimensional integrated circuits (3D ICs) built with through-silicon vias (TSVs) have smaller footprint area, shorter wirelength, and better performance than 2D ICs. However, the quality of 3D ICs is strongly dependent on TSV dimensions and parasitics. Using large TSVs may cause silicon area overhead and reduce the amount of wirelength reduction in 3D ICs. In addition, non-negligible TSV parasitic capacitance can result in delay overhead affecting the delay of 3D ICs. Meanwhile, with the development of TSV manufacturing technology, nano-scale TSVs are emerging, which is expected to reduce the overheads caused by using large TSVs. Therefore, this paper investigates the impact of nano-scale TSVs on the quality of 3D ICs at future technology nodes. For this study, we develop a 16nm standard cell library, design 3D ICs using different process technologies (45nm, 22nm, and 16nm) and various TSVs diameters (from 5μm to 0.1μm), and discuss the impact of nano-scale TSVs.
منابع مشابه
13th Int'l Symposium on Quality Electronic Design
Bias temperature instability (among other problems) is a key reliability issue with nanoscale CMOS transistors. Especially in sensitive circuits such as sense amplifiers of SRAM arrays, transistor aging may significantly increase the probability of failure. By analyzing the Current Based Sense Amplifier circuit and Voltage-Latched Sense Amplifier circuit through HSPICE simulations, we observe t...
متن کامل13th Int'l Symposium on Quality Electronic Design
The Network-on-Chip (NoC) is an enabling technology to integrate large numbers of embedded cores on a single die. Traditional multi-core designs based on the NoC paradigm suffer from high latency and power dissipation due to the inherent multi-hop nature of communication. The performance of NoC fabrics can be significantly enhanced by introducing long-range, low power, and high-bandwidth single...
متن کامل13th Int'l Symposium on Quality Electronic Design
A post-fabrication dual supply voltage (VDD) control (PDVC) of multiple voltage domains is proposed for a minimum operating voltage (VDDmin)-limited ultra low voltage logic circuits. PDVC effectively reduces an average VDD below VDDmin, thereby reducing the power consumption of logic circuits. PDVC is applied to a DES CODEC’s circuit fabricated in 65nm CMOS. The layout of DES CODEC’s is divided...
متن کامل13th Int'l Symposium on Quality Electronic Design
In modern VLSI circuits, a large number of clock buffers are inserted in clock distribution networks, which are significantly affected by process and power supply noise variations. The combined effect of process variations and power supply noise on clock skew and jitter is investigated in this paper. A statistical model of skitter, which consists of skew and jitter, is proposed. Clock paths wit...
متن کامل13th Int'l Symposium on Quality Electronic Design
Experimental results of an active filter based onchip hybrid voltage converter are described in this paper. The area of the voltage converter is significantly less than the area of a conventional passive filter based DC-DC voltage converter or a low-dropout (LDO) regulator. Hence, the proposed circuit is appropriate for point-of-load voltage regulation for the noise sensitive portions of an int...
متن کامل